Technical Field
The present disclosure relates to a semiconductor circuit in a semiconductor integrated circuit, a voltage detection circuit, and a voltage determination circuit.
Related Art
Conventionally, power-on reset circuits that detect turning-on and shutdown of a power supply in a semiconductor integrated circuit, and that generate reset release signal or a reset signal in the semiconductor integrated circuit, have been used (for example, see Japanese Patent Application Laid-Open (JP-A) No. 2011-86989). FIG. 17 illustrates an example of the conventional power-on reset circuit. Hereinafter, a description will be made regarding a configuration and an operation of the conventional power-on reset circuit with reference to FIG. 17.
First, regarding the configuration, the conventional power-on reset circuit is configured by a detection block C1 including a PMOS transistor P1 of which a gate is connected to GND, and an NMOS transistor N1 of which a gate is connected to BIAS to be input from an external bias circuit, and a detection block C2 including the same configuration, and a logic circuit, as illustrated in FIG. 17.
Here, the PMOS transistor P1 included in the detection block C1 and a PMOS transistor P2 included in the detection block C2 are configured using transistors having different threshold values. A threshold Vtp1 of the PMOS transistor P1 and a threshold Vtp2 of the PMOS transistor P2 are set such that Vtp1<Vtp2.
In addition, the NMOS transistor N1 included in the detection block C1 and an NMOS transistor N2 included in the detection block C2 function as constant current sources when a constant voltage is applied to each gate from the external bias circuit.
Next, the operation will be described with reference to an operation waveform of the conventional power-on reset circuit illustrated in FIG. 18.
First, when a power supply VDD becomes equal to or higher than the threshold of the PMOS transistor P1 during a rise of the power supply VDD, the PMOS transistor P1 is turned ON, and the detection block C1 outputs an H-level.
At this time, the detection block C2 outputs an L-level, input of an RS latch configured of a two-input NOR circuit L6 and a two-input NOR circuit L7, a node n1 and a node n2 become states as illustrated in FIG. 18, and an output OUT becomes the H-level having a voltage level Von along with switching of the node n1.
Similarly, during a fall of the power supply VDD, the output OUT becomes the L-level having a voltage level Voff along with switching of the node n2.
In this manner, the conventional power-on reset circuit is configured to detect different voltages using the two detection blocks.
However, in the conventional power-on reset circuit illustrated in FIG. 17, it is necessary to provide the MOS transistors having the two types of threshold values so as to set different power-on reset threshold voltages between the rising state and the falling state of the power supply. Accordingly, the number of steps in a semiconductor process increases, and further, a circuit size and current consumption increase together, since it is necessary to provide the two detection blocks in the power-on reset circuit.